AIE or EIS 

FIE 

DMA 

M1 

Interrupt Function 

0 

X 

1 

0 

No interrupt generated.
Poll INT to determine when a DMA terminal count is received from the DMA controller to indicate completion of the DMA transfer. 

1 

X 

0 

0 

Interrupt generated when an ADC conversion has completed. Write to the Clear Interrupt Register to clear the interrupt. In DAS1602 compatibility mode (jumper M0 installed), an interrupt is generated for each sample when in ADC-burst mode. 

1 

X 

1 

0 

Interrupt generated when a DMA terminal count is received from the DMA controller to indicate completion of the DMA transfer. 

0 

0 

0 

1 

No interrupt generated.
Poll INT to determine when an ADC conversion has completed.
Poll INT_FF to determine when 512 additional samples have been queued to the FIFO. The number of blocks is now configurable, refer to the Interrupt Configuration Register.
 

0 

X 

1 

1 

No interrupt generated.
Poll INT to determine when a DMA terminal count is received from the DMA controller to indicate completion of the DMA transfer.
Poll INT_FF to determine when 512 additional samples have been queued to the FIFO. The number of blocks is now configurable, refer to the Interrupt Configuration Register.
 

1 

X 

1 

1 

Interrupt generated when a DMA terminal count is received from the DMA controller to indicate completion of the DMA transfer. 

0 

1 

0 

1 

Interrupt generated when 512 additional samples are deposited in the FIFO. Write to the Clear Interrupt Register to clear the interrupt. The number of blocks required to generate an interrupt is now configurable, refer to the Interrupt Configuration Register.

Poll INT to determine when deglitched DIN0 rising-edge has occurred. By connecting CT_OUT0 or CT_OUT2 to DIN0 you can create a polled timing function. Any external input can produce a polled rising-edge. If GCTRL bit is set then this can be used to detect the beginning of pacer clock gating (i.e. start of one or more samples). Writing to the Clear Interrupt Register will also clear the INT bit.
 

1 

0 

0 

1 

Interrupt generated when an ADC conversion has completed. Write to the Clear Interrupt Register to clear the interrupt. In DAS1602 compatibility mode (jumper M0 installed), an interrupt is generated for each ADC-burst completion when in ADC-burst mode.
Poll INT_FF to determine when 512 additional samples have been queued to the FIFO. The number of blocks is now configurable, refer to the Interrupt Configuration Register.
 

1 

1 

0 

1 

Interrupt generated when 512 samples deposited in the FIFO. Write to the Clear Interrupt Register to clear the interrupt. The number of blocks required to generate an interrupt is now configurable, refer to the Interrupt Configuration Register.
Interrupt generated when deglitched DIN0 rising-edge has occurred. By connecting CT_OUT0 or CT_OUT2 to DIN0 you can create an interrupt timing function. Any external input can produce an interrupt. If GCTRL bit is set then this can be used to detect the beginning of pacer clock gating (i.e. start of a group of samples). Writing to the Clear Interrupt Register will also clear the INT bit.