FIFO Configuration (Index=228, RB='1')

FIFO Configuration Register

Index=0xE4, Byte 0. RB='1'.

D7	D6	D5	D4	D3	D2	D1	D0
HSFIFOEN	X	X	X	X	X	X	X

Bit Definitions

NAME	DIRECTION	DEFAULT	DESCRIPTION
X	-	-	Don't Care
HSFIFOEN	rw	0	High Speed pre-queue FIFO Buffer Enable 0 = Disabled, utilize main memory only (default) 1 = Enabled, use high speed CPU buffer

Description

Enabling the High Speed CPU FIFO Buffer can reduce bus wait states generated due to waiting for STX104 main memory data availability. In many cases, bus wait states (due to IOCHRDY) are eliminated. We found that overall throughput through the ISA bus was improved by approximately 15%.

By default the CPU FIFO Buffer is disabled in order to maintain classic timing characteristics which might be critical to a customer completed application.