The STX104 now supports CPU cards which only present the first 10 address lines. Normally, the STX104 will decode all 16 address bits in order to fully decode an I/O command. For 10-bit address decode, the upper 6 address bits are ignored. A 10-bit address decode provides a typical I/O address space from 0x000 to 0x3FF. The DAS1602 burst registers are now alternatively available through indexed register array access. 

The STX104 is compatible with DAS16jr/16 and the DAS1602. The DAS16jr/16 mode supports 8-bit or 16-bit systems (XT or AT, respectively). The enhanced register set now supports redirection of the DAS1602 extended burst registers to the indexed array register set thus allowing more addressing and data width options including both XT and AT compatibility. Jumper position M0 selects one of these compatibility modes. 

The DAS1602 compatibility offers ADC-sample and ADC-bursting. 

Data FIFO superset functionality can be selected for either the DAS16jr/16 or the DAS1602 compatibility modes. The FIFO superset functionality is very similar to other cards on the market. Stuffing jumper position M1 enables FIFO superset functionality. Note that for the DAS1602 compatibility mode, the 1 mega-sample FIFO is enabled, however to maintain register compatibility the FIFO status registers are only visible once the M1 jumper is installed. 

The HSFIFOEN bit found in the FIFO Configuration register can be used to enable a 2048 sample high speed pre-queueing FIFO buffer between STX104 main memory and the ISA bus. In general, this will reduce/eliminate IOCHRDY wait states and improve average system throughput. 

The 16-bit DAC mode allows the DAC registers to provide 12-bit legacy functionality as well as full 16-bit DAC functionality. Stuffing jumper M2 allows for full 16-bit DAC operation. 

Installing jumper M3 enables the 16-sample moving average filter for all channels. The filter can be reset (or cleared) by writing to the Channel Register. The moving average filter is enabled for all channels and operates completely transparent to ADC acquisition modes. The ADC values read out will be the current sample plus the last fifteen samples summed together and divided by sixteen (average of sixteen ADC samples). It is important to recognize that after the filter is reset or at the beginning of data sampling that it may require at least 16-data samples per channel be taken until the data becomes current. In other words, there is an inherent 16-sample delay in the ADC data that is read out of the ADC Data Register. 

Note: 1 = Jumper installed, 0 = Jumper not installed.

Hardware Configuration