D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

CNV 

UB 

SD 

INT 

TAS 

FF_INT 

ISSB 

ISSA 

D7 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

CNV 

UB 

SD 

INT 

CH3 

CH2 

CH1 

CH0 

NAME 

DIRECTION 

DEFAULT 

DESCRIPTION 

CNV 

r 

0 

ADC Conversion (and/or ADC-Burst in DAS1602 mode) in progress. Writing to the Channel Register may cause the CNV bit to become active indicating that a STX104 internal reset is in progress (typically less than 1uS, and less than 10uS when moving average filter is enabled).
1 = ADC conversion, scan or acquisition reset in progress.
0 = ADC Idle (default) 

UB 

r 

- 

Unipolar / Bipolar ADC input mode setting (J9):
0 = bipolar. Measure both negative and positive input
voltages (J9 not stuffed)
1 = unipolar. Measure only positive input values 

SD 

r 

- 

Single-ended / Differential ADC input mode setting (J8):
0 = Single-ended
1 = Differential (J8 not stuffed) 

INT 

r 

0 

Interrupt request status bit.
0 = No interrupt pending (default)
1 = Interrupt is pending; ADC trigger or ADC-Burst conversion
has completed
Note: ADC conversions continue to occur on schedule (via selected trigger source) regardless of whether this bit is cleared. If a new conversion occurs before this bit is cleared, an over-run condition may have occurred. Therefore, the programmer must ensure that the interrupt rate is not faster than the capacity of the CPU and software to respond.
If FIFO Superset is enabled (jumper M1 stuffed), then the only over-run that will occur is if the FIFO is full (FIFO Full flag is true or FF=’1’). Thus, interrupt latency requirements are greatly relaxed.
If ADC interrupts are not enabled, this bit can still be used to determine when an ADC conversion has occurred when polling this bit. 

CH[3:0] 

r 

0000 

Current ADC channel. This is the channel currently selected on the board and is the channel that will be used for the next ADC conversion provided CNV=0 (unless a new value is written to the channel register). The CH[3:0] will change shortly after an ADC trigger. 

TAS 

r 

0 

Trigger Activity State. This is the same status bit as the TRG bit found in the ADC Configuration Register. The trigger status is provided here so that interrupt and board status can be read as one value, thus keeping an interrupt service routine short as possible.
0 = trigger inactive (default)
1 = trigger active 

FF_INT 

r 

0 

FIFO Interrupt Status (Please refer to FIFO Status MSB Register for further details):
0 = Not Active
1 = Interrupt Active 

ISSB 

r 

0 

Interrupt Status Source B:
0 = Not Active
1 = Interrupt Active 

ISSA 

r 

0 

Interrupt Status Source A:
0 = Not Active
1 = Interrupt Active 

X 

- 

- 

Don't Care