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ADC Configuration (Offset=11)
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ADC Configuration Register

Register Layout

 

Offset=0xB, Byte 0. Write Only Pattern.  

D7 
D6 
D5 
D4 
D3 
D2 
D1 
D0 
RBK3 
RBK2 
RBK1 
RBK0 
X 
X 
GAIN1 
GAIN0 

 

Offset=0xB, Byte 0. Read Only Pattern.

D7 
D6 
D5 
D4 
D3 
D2 
D1 
D0 
RB 
X 
X 
X 
TRG 
ADBU 
GAIN1 
GAIN0 
Bit Definitions
NAME 
DIRECTION 
DEFAULT 
DESCRIPTION 
RB 
r 
0 
Register Bank Status (only available in Enhanced Register Mode):
0 = 8254 Counter/Timer Bank Active (default)
1 = Indexed Register Array Bank Active 
RBK[3:0] 
w 
8254 Bank 
Register Bank Key Select (only available in Enhanced Register Mode). Writing a special sequence will bank select either the 8254 counter/timer or an Indexed Register Array Set. The default state is always with the 8254 bank selected (i.e. original register set configuration).

1111 --> 0101 --> 1101 F 5 D
0011 --> 1011 --> 1010 3 B A

Writing the sequence 0xFX, 0x5X, 0xDX will enable the Indexed Register Array Bank. Writing the sequence 0x3X, 0xBX, 0xAX will disable the Indexed Register Array Bank. The sequences preserve upward compatibility and ensure that the bank select remains set even under existing software activity. 
TRG 
r 
0 
Trigger Activity State. This same status bit is available at the ADC Status Register TAS bit. This bit is available here as well in the event that classic interrupts are required which would make the TAS bit unavailable.
0 = trigger inactive (default)
1 = trigger active 
ADBU 
r 
depends on J9 
ADC bipolar/unipolar:
0 = bipolar setting (jumper J9 not installed)
1 = unipolar setting
 
GAIN[1:0] 
rw 
00 
ADC gain setting:
00 = gain of x1 (default)
01 = gain of x2
10 = gain of x4
11 = gain of x8
 
X 
- 
- 
Don’t care 
Description
REGISTER BANK SELECT

Register Bank Select is a mechanism for providing additional configuration options for the STX104, while preserving the existing register set foot-print within the I/O space. Writing the sequence 0xFX, 0x5X, 0xDX will enable the Indexed Register Array Bank. Writing the sequence 0x3X, 0xBX, 0xAX will disable the Indexed Register Array Bank. Writing any other sequence will not change the state of the register bank. The sequences preserve upward compatibility and ensure that the bank select remains set even under existing software activity. Bank select can be verified by reading the RB bit shown above. 

 

GAIN SUMMARY

Writing to this register sets the analog input gain for all 8/16 analog inputs. The ADBU bit is set by hardware. The current input gain is determined by reading this register. 

 

INPUT RANGE 
RESOLUTION 
ADBU 
G1 
G0 
+/- 10 V 
305 uV 
0 
0 
0 
+/- 5 V 
153 uV 
0 
0 
1 
+/- 2.5 V 
76 uV 
0 
1 
0 
+/- 1.25 V 
38 uV 
0 
1 
1 
0 - 10 V 
153 uV 
1 
0 
0 
0 - 5 V 
76 uV 
1 
0 
1 
0 - 2.5 V 
38 uV 
1 
1 
0 
0 - 1.25 V 
19 uV 
1 
1 
1 

 

The ADC data range is –3276810 to 3276710 for each of the input ranges listed below. 

See the software example in the ADC Data Register section earlier in this chapter. 

The gain setting is the ratio between the ADC full-scale range and the effective input signal range. For example, if the ADC full-scale range is 0-10V, a gain setting of 2 creates an input signal range of 0-5V, and gain setting of 4 creates an input range of 0-2.5V.

See Also
BANKING BETWEEN 8254 AND THE INDEXED REGISTER ARRAY
/*****************************************************************
/                                      SET BANK 8254/INDEXED-ARRAY
/
/ Call this function when changing from one bank to another.  Recommend only
/ changing the bank when one read/writes to the 8254, since that is likely to
/ be read/written to the least amount compared to the indexed register array.
/
/ Alternatively, one could check the RB bit each time an indexed register
/ is read or written; it will then take longer on average to read/write registers.
*/
void STX104_Set_Bank( int board, char bank )
{
    unsigned char scratch;
    unsigned char value;
    unsigned int address;

    address = stx104_base_address[board] + STX104_ADC_CONFIGURATION;
    scratch = inp( address );
    if ( bank == 0 ) /* request banking to the 8254 */
    { /* test for RB bit in ADC configuration register */
        if ( (scratch & 0x80) == 0x80 )
        {
            scratch = scratch & 0x0F;
            value = scratch | 0x30;
            outp( address, value );
            value = scratch | 0x30;
            outp( address, value );
            value = scratch | 0xB0;
            outp( address, value );
            value = scratch | 0xA0;
            outp( address, value );
        }
    }
    else
    {   /* request banking to the indexed register array */
        if ( (scratch & 0x80) == 0 )
        {
            scratch = scratch & 0x0F;
            value = scratch | 0xF0;
            outp( address, value );
            value = scratch | 0xF0;
            outp( address, value );
            value = scratch | 0x50;
            outp( address, value );
            value = scratch | 0xD0;
            outp( address, value );
        }
    }
}
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Copyright © 1997-2008 by Apex Embedded Systems. All rights reserved. Updated on Wednesday, April 02, 2008.
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