ADC Channel (Offset=2)

ADC Channel Scan Register

Offset=0x2, Byte 0.

D7	D6	D5	D4	D3	D2	D1	D0
LC3	LC2	LC1	LC0	FC3	FC2	FC1	FC0

Bit Definitions

NAME	DIRECTION	DEFAULT	DESCRIPTION
CH[3:0]	r	0000	Current Channel to be sampled. See ADC Status Register. This value is sent to the analog multiplexers to set the current analog channel to be sampled. This value can be read in the ADC Status Register. Shown here for completeness only.
FC[3:0]	rw	0000	First Channel. This is the first analog channel that is sampled. When this value is written, it will also set the current-channel ( CH = FC ).
LC[3:0]	rw	0000	Last Channel. This is the last analog channel that is sampled. Once this channel has been sampled, the current-channel value will wrap to the first-channel value.

Description

The channel register contains first-channel and the last-channel in the scanning range of the analog multiplexer. When the channel register is written the first-channel value is also written to the current-channel which sets the analog channel to be sampled. Upon an ADC trigger, the ADC samples the current-channel, and the multiplexer is advanced to the next channel. The current-channel value will wrap from the last-channel to the to the first-channel once the last-channel as been sampled.

The current-channel value is incremented only when the ADC is sampled or triggered. For every ADC trigger, the current-channel is incremented. The current-channel is presented as CH[3:0] in the ADC Status Register.

If the STX104 is configured for differential input mode, the most significant bit of the current-channel (and therefore first- and last-channel) is ignored.

If the FIFO function is enabled, the user software must track the channel being read out of the FIFO. In other words, it is the software which must maintain synchronization.

If the first-channel is the same as the last-channel, then the analog channel (multiplexer) is not changed. This can be useful for sampling the same channel continuously.

It is recommended to have first-channel < last-channel to prevent confusion of the channel sequencing as illustrated in examples (C) and (D) below.

FIFO RESET

Writing to the channel register will reset the FIFO when the FIFO Superset mode is enabled (jumper M1 is installed) and/or DAS1602 mode enabled (jumper M0 is installed).

ACQUISITION CONTROLLER RESET

Writing to the Channel Register resets the internal acquisition controller in all modes.

MOVING AVERAGE FILTER RESET

Writing to the Channel Register also resets the internal moving average filter in all modes when jumper M3 is installed. The CNV bit (see ADC Status Register) will become active for approximately six microseconds while the moving average filter is reset.

SS&H OUTPUT

The Start Sample and Hold (SS&H) signal, at pin 14 of the I/O connector, is a TTL output used to drive the sample and holds line of external simultaneous sample and hold cards. The behavior of the SS&H output signal is related to the Channel Register. Writing any value to the Channel Register will bring the SS&H line active high. The SS&H line will go low, indicating a hold, when the first_channel sampling has completed (i.e. the input multiplexers now looking at the next channel). The SS&H line will return high when last_channel has been sampled and the multiplexers wrap back to the first_channel.