8254 Configuration (Offset=15, RB='0')

8254 Configuration Register

Offset=0xC, RB='0'. 8254 Counter/Timer Zero Data Register.This register is available when Register Bank Status is '0' (see ADC Configuration Register bit RB).

D7	D6	D5	D4	D3	D2	D1	D0
CT0D7	CT0D6	CT0D5	CT0D4	CT0D3	CT0D2	CT0D1	CT0D0

Offset=0xD, RB='0'. 8254 Counter/Timer One Data Register.

D7	D6	D5	D4	D3	D2	D1	D0
CT1D7	CT1D6	CT1D5	CT1D4	CT1D3	CT1D2	CT1D1	CT1D0

Offset=0xE, RB='0'. 8254 Counter/Timer Two Data Register.

D7	D6	D5	D4	D3	D2	D1	D0
CT2D7	CT2D6	CT2D5	CT2D4	CT2D3	CT2D2	CT2D1	CT2D0

Offset=0xF, RB='0'. 8254 Counter/Timer Configuration Register.

D7	D6	D5	D4	D3	D2	D1	D0
SC1	SC0	RW1	RW0	M2	M1	M0	BCD

Bit Definitions

NAME	DIRECTION	DEFAULT	DESCRIPTION
CT0D[7:0]	rw	-	8254 Counter/Timer Zero Data Register
CT1D[7:0]	rw	-	8254 Counter/Timer One Data Register
CT2D[7:0]	rw	-	8254 Counter/Timer Two Data Register
SC[1:0]	w	-	Select Counter: 00 = Select Counter 0 01 = Select Counter 1 10 = Select Counter 2 11 = Read-Back Command (see read operations)
RW[1:0]	w	-	Read/Write: 00 = Counter latch command 01 = Read/Write least significant byte only 10 = Read/Write most significant byte only 11 = Read/Write least significant byte first, then most significant byte.
M[2:0]	w	-	Counter/Timer Mode Select: 000 = Mode 0, Interrupt on terminal count 001 = Mode 1, Hardware retriggerable one-shot X10 = Mode 2, Rate generator X11 = Mode 3, Square wave generator 100 = Mode 4, Software triggered strobe 101 = Mode 5, Hardware triggered strobe (retriggerable)
BCD	w	-	Binary Coded Decimal (BCD) Counter (4 decades) if set to one, otherwise 16-bit binary counter.

Description

This register is available when Register Bank Status is '0' (see ADC Configuration Register bit RB).

See Also

ADC Configuration Register

8254 Data Sheet

Example

/*****************************************************************
/                           ANALOG INPUT 8254 COUNTER 1 & 2 TIMING
*/
static void STX104_AI_Timing_8254_Set( int board, long time_interval_ns )
{
    long high_count;
    long low_count;
    unsigned int octet;

    STX104_Set_Bank( board, 0 );

    /* assumes 10MHz clock (i.e. no 1MHz jumper) */
    low_count  = 10L; /* 1 microsecond intervals */

    high_count = time_interval_ns / 1000;
    while ( high_count > 65536L )
    {
        high_count = high_count >> 1;
        low_count  = low_count << 1;
    }
    while ( high_count < 2L )
    {
        high_count = high_count << 1;
        low_count  = low_count >> 1;
    }
#ifdef STX104_DEBUG_MODE
     fprintf( stdout, "low_count=%ld, high_count=%ld\n",low_count,high_count);
     fprintf( stdout, "Actual Interval (uSec) = %ld\n",time_interval_ns);
#endif
    /* set counter/timer 2  */
    outportb( stx104_base_address[board] + STX104_CT_CONFIGURATION, 0xB4 );
    octet = ((unsigned int) high_count) & 0x00FF;
    outp( stx104_base_address[board] + STX104_CT2_DATA, octet );
#ifdef STX104_DEBUG_MODE
    fprintf( stdout, "CT2 LB=%u\n",octet );
#endif
    octet = ((unsigned int) high_count) >> 8;
    outp( stx104_base_address[board] + STX104_CT2_DATA, octet );
#ifdef STX104_DEBUG_MODE
    fprintf( stdout, "CT2 HB=%u\n",octet );
#endif
    /* set counter/timer 1  */
    outportb( stx104_base_address[board] + STX104_CT_CONFIGURATION, 0x74 );
    octet = ((unsigned int) low_count) & 0x00FF;
    outp( stx104_base_address[board] + STX104_CT1_DATA, octet );
#ifdef STX104_DEBUG_MODE
    fprintf( stdout, "CT1 LB=%u\n",octet );
#endif
    octet = ((unsigned int) low_count) >> 8;
    outp( stx104_base_address[board] + STX104_CT1_DATA, octet );
#ifdef STX104_DEBUG_MODE
    fprintf( stdout, "CT1 HB=%u\n",octet );
#endif
}

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